within a single monolithic chip is now enabling the offload of power-hungry FPGA resources to allow for a smaller footprint, lower power, increased channel count platforms that can sample at higher rates than previously achievable. Along with this new capability comes novel multichip synchronization (MCS) algorithms within these integrated circuits (ICs), which allows users to achieve a known (deterministic) phase for all channels when powering the system or otherwise making software modifications to the system. This deterministic phase, therefore, simplifies the broader system-level calibration algorithms needed to achieve the synchronization of all channels at the output or input to the front-end networks attached to these ICs. This article presents experimental results that demonstrate this MCS capability while using a 16-channel receiver/transmitter platform consisting of multiple digitizer ICs, clock sources, and digital interfaces.
Power up phase determinism using multichip synchronization.
within a single monolithic chip is now enabling the offload of power-hungry FPGA resources to allow for a smaller footprint, lower power, increased channel count platforms that can sample at higher rates than previously achievable. Along with this new capability comes novel multichip synchronization (MCS) algorithms within these integrated circuits (ICs), which allows users to achieve a known (deterministic) phase for all channels when powering the system or otherwise making software modifications to the system. This deterministic phase, therefore, simplifies the broader system-level calibration algorithms needed to achieve the synchronization of all channels at the output or input to the front-end networks attached to these ICs. This article presents experimental results that demonstrate this MCS capability while using a 16-channel receiver/transmitter platform consisting of multiple digitizer ICs, clock sources, and digital interfaces.
